Travelling On The Silicon Road

In October 2005, John Chambers, Chairman and CEO Cisco Systems had announced a 1.1 B$ investment in India. In his recent visit to India last week, he re-iterated Cisco’s commitment while outlining the importance of India in Cisco’s global growth strategy.

Cisco’s key investments in India include a new R&D campus in Bangalore, increasing by threefold its local workforce, launching a manufacturing pilot facility for local market and allocating funds for venture capital investments in high growth and nascent companies based in India. Investments are expected in companies involved in broadband content and digital media.

All these are in line with John’s vision of the network becoming the platform for all forms of communication and ICT – also the topic of his interesting talk in Singapore last Friday.

Qualcomm, with its IFM (Integrated Fabless Manufacturing) strategy is quietly but steadily decreasing the gap between itself and IDMs in new process adoption time. The world’s largest fabless design company is leading the way in how the fabless design community needs to overcome the DSM hurdles of the widening gaps between IC design and manufacturing flows.

While not exactly striving to be process experts, Qualcomm has formed a virtual manufacturing organization including its VLSI Technology organization and DFX unit which has helped it to understand, appreciate and thus resolve a host of complex and costly issues. The results, closing of the technology gap with the IDMs, are the proof.
They are cautious enough, though, as to not necessarily be the first ones to ship out a new product on a new technology node.

With Paul Jacobs’ strategy of making people understand that Qualcomm is a wireless technology company and not just a CDMA company, it needs all the efforts and results to zoom to the next node in a competitive manner.

Atheros recently picked up Attansic Technology, a designer of Ethernet chips in Taiwan for its Gigabit Ethernet technology for 802.11n market. Attansic is a subsidiary of Asustek. Craig Barratt, CEO of Atheros said, “there has really been tremendous growth in companies in Taiwan doing pretty impressive R&D, creative engineering and product development.”

Moving to India – India needs to include IPs and technology know-how into their growing expertise portfolio. As I mentioned in an earlier post, product know-how is essential for the differentiating factor. With its relatively better copyright rules as compared to China for example, if the Indian companies can supplement their design skills and embedded software expertise with the product & technology know-how, they can raise the stakes higher.

There are some examples like Wipro, Tejas Networks etc. but it’ll be good to see this list grow.

From what had earlier started as point engagements or doing auxillary services, semiconductor design companies in India are now working on not only the leading edge technologies (which they were still doing in the past as point engagements) but also end to end projects. In doing so, the Indian design engineers have been able to broaden their skill set as compared to quite a few of their international counterparts.

When you don’t have the so called luxury to specialize in certain niches areas and are thrust with the responsibility of doing multiple design tasks in order to get a design out, well, one learns and that too fast! A positive go-getter attitude coupled with a survival instinct honed by the competitive Indian environment (which starts right from kindergarten) also does help.

The early 90’s saw design companies in India getting supplementary work albeit some in leading edge technology. Of course, cost was the major reason. Once they instilled some confidence, it morphed into a bigger part of the design cycle. They started getting not only more designs but the opportunity and the responsibility to execute a design end to end and also complex designs. However technology innovations have still not figured within their purview.

Attrition: While this rate is high and experienced engineers switch jobs, money is not always the major deciding factor. Generically speaking, fresh graduates/ engineers with a couple of years experience rate the work quality and the company branding more than money. Mid range experience engineers value work quality, responsibilities and money. Professionals who return to India after working abroad are looking for challenging opportunities. I am not saying that money is not significant but rather that if the employee retention logic is through money alone, well, mate, you are throwing the wrong carrot…Indians have always had an entrepreneurial spirit (I attribute it to the urge to remove the shackles, something linked with our political history as well as the present political scenario).

Design ecosystem: While some may say that the absence of fabs is not a hindrance to the design scene in India, the fact remains that SoCs of today are not just built on design flow, IPs and library know how. One needs to have the product know how too – and this can become a major differentiating factor. And of course, trying out a new design concept in one country, fabricating in another and waiting for it to come back in order to do the tests, not to mention the red tape which may be involved, is something which one can do without. One of the reasons why Taiwan grew to a semiconductor hub is that it had design, fabrication, packaging and testing right there. So, while presently it may not sound so much of a missing link, it will gain importance if India is to take up China.

The above article was preceded, by just a couple of days, by another article appearing in Electronic business cited India’s niche: semiconductor design services. So if the talents void increases, India risks losing the niche.

As pointed out in the article, most designers treat IP as a product. However, this product rarely comes with a guarantee; which is not that surprising. It’ll be almost suicidal given the argument that IPs are not plug in objects. Not only the IP’s functionality but also its interface and integration with the other components in the system determine whether the chip will work or not. And a standalone guarantee for an IP does not hold much credence.

A close working relationship between IP supplier and user has always been deemed vital for the successful IP usage and integration; hence to formalize it and bundle things under the “service” umbrella will not be that major a leap of faith.

China Syndrome cooling, an article by Ed Sperling in Reed Electronics points out the possible waning of the “Invest in the Booming China Market” wave by electronics companies. Possible reasons cited by them for hedging their bets in other regions and in other countries include:

- China’s emphasis on allowing other cities besides Shanghai and Beijing to partake in the economic revolution is making it far more difficult for companies to manage logistics between their manufacturing sites inside of China;

- Rapidly rising labor costs are forcing some companies to consider comparable wage scales in places such as Vietnam, Malaysia and Eastern Europe;

- China’s ineffective policing of intellectual property theft has made many companies reluctant to move design operations there;

- Continued U.S. government regulations about what technology can be shipped into China or developed there has kept the lid on many companies’ plans;

- Manufacturers are looking to hedge their bets with backup strategies in case of a natural disaster or political issues that can affect regions.

Well, it makes economic and political sense for China’s emphasis to let its cities other than Shanghai and Beijing to invite investments so that they can have an inclusive growth – something vital for both the economic and political stability of a country else the economic disparity thus created would mitigate the growth achieved otherwise. To help the electronics companies, infrastructure improvement in these other cities could help.

Ineffective policing of IPs is indeed an important deterrent. However a few recent events are providing some progress. Hong Kong Science and Technology Parks Corporation (HKSTP) recently inaugurated the Intellectual Property Servicing Centre (IPSC) at the Hong Kong Science Park. Based within the Hong Kong Integrated Circuits Design Centre at the Park, it offers IP licensing, IP hardening, IP integration and IP verification services. Most notably, IPSC is run by HKSTP and will make use of Hong Kong law for any legal dispute over intellectual property. A key vehicle for this will be the Hong Kong International Arbitration Centre which is based in the SAR.

Under the “7+1” IC Design Centre framework signed with the High-Technology Research & Development Centre of the PRC’s Ministry of Science & Technology, HKSTP jointly collaborated with Harbin Institute of Technology, Hefei University of Science and Technology, Zhejiang University and the Hong Kong University of Science and Technology in July 2005 to extend the SIP trading platform throughout Greater China. The collaboration is to develop a due diligence platform in legal and technical terms for SIP certification and authentication purposes.

In October 2005, HKSTP also formed alliance with the China’s Ministry of Information Industry Software and Integrated Circuit Promotion Centre (CSIP) for the Mainland China IC design industry. The alliance is to promote the cooperation and development of Mainland China’s IC enterprises under the guidance and supervision of the administrative bodies, to jointly facilitate the outreach and popularization of SIP in SoC design services, as well as to standardize the SIP design, SIP standard promotion and SIP protection mechanism.

Gartner during it’s mid year update outlined 5 megatrends facing the industry - continued integration due to Moore’s Law, increasing cost and scale of manufacturing facilities, the role the consumer markets will have going forward, service providers of various kinds, and a set of new and potentially disruptive technologies.

One more major trend that I perceive, is increasing collaboration. Whether it is OEMs collaborating with service providers or EDA companies/Design houses with foundries, this collaboration will increase. This is especially true for deep sub micron technologies.

Fewer chip designs will also re-enforce EDA companies to rethink their strategies and biz models. They will need to address solutions. As pointed out by Robert Hum/Mentor Graphics, “it is time for a change”. For verification, for example, realization of the methodology flow within the common & open source verification environment by solutions and not just point tools should be the offerings from the EDA vendors. An open source community which leverages on the combined industry expertise is the need. However such open source platforms take time to be adopted as players approach it warily keeping their IPs and niche expertise in mind.

Technology innovations will continue, in fact grow faster. There will also be increase in the number of startups with each one of them trying to address some niche area in the market and trying to tap it in the mode they think best. However as pointed out by Gartner, the question is how many will survive the transitions.

Another outcome of fewer chip makers in the market due to increase in manufacturing scale will be the diminishing of manufacturing differentiation.

The market has moved more from standalone products to solutions. And solutions go hand in hand with service thus getting the service providers into a more prominent role. Service providers are nearer to the end customer and know their requirements which will also propel them towards a product defining role.

The growing power of the consumer market and keeping in mind its demands, will lead to more reconfigurable devices. The challenge, however, will be keeping the costs down as reconfigurability does not come with optimized silicon usage.

Yes, indeed the methodology should be done by people who know it best i.e. design engineers. EDA companies should step in to facilitate this and not formulate them. We should not have situations where the design engineer needs to grapple with firstly the design & process complexities and secondly with trying to fit the design tool into his design methodology. With the increasing complexities associated with sub micron designs, there is a need for more and more collaboration. The tasks are too mammoth and interlinked for any single entity to manage on their own. Realization of the methodology flow within the common & open source verification environment by solutions and not just point tools should be the offerings from the EDA vendors. Indeed an open source community which leverages on the combined industry expertise is the need. However such open source platforms take time to be adopted as players approach it warily keeping their IPs and niche expertise in mind.

Yes, it indeed is true that the real assets of a company are it’s intellectual capital. Not being tangible in the conventional manner, this is not analysed to the extent it merits.

Increasing your market share without upsetting your profit margin ; and all this while not letting your intellectual capital diminish is indeed a juggling act. While globalization pushes companies to compete internationally against lower paying work forces, it also throws open the option of getting work done not only cost effectively but also Qualitatively.

We start with a lean organization with the core people – the identified and nurtured intellectual capital. Identify all the work/activities which can be outsourced. Give it to smaller companies which focus on that specific activity. Tap on the freelancers specializing in niche areas. We do see this in the present scenario too e.g. design houses, foundries, testing, distributors etc. However, the synergy here needs to be channeled and optimized. With global work forces, anyhow geographical barriers are falling. It’s pay per usage. The core employees formulate the strategies, give directions for the company’s growth and manage this knowledge bank of smaller companies and free lance professionals.

There are quite a few challenges to this approach but I do not think they are unmanageable. The biggest one would be IP protection. But then, that hasn’t deterred much the design activities or technology development/transfer to places like China. The recent panel on IP in China moderated by the president of SIA and as reported in Electronics News by Suzanne Deffree (dt. 3/3/2006) cites - China has the intellectual capability and the numbers. Barriers are not going to work. We have to try to safely enable them.

Both ASIC and COT designs need the designer to fix the foundry at the onset. This is because the library and the design rules needed for both are supplied by the target foundry. COT, however, does have the flexibility for changing the foundry at a later stage provided the process is compatible across multiple foundries – however it still needs some verification to avoid problems on silicon. Multiple sources especially where one needs backups and also an advantage for price negotiations have been in the picture.

DFM does change a lot of value propositions. COT’s have been less costly not just because foundries compete on price but also because the extra service of design implementation in an ASIC comes with it’s own price tag. With DFM, the boundary between design and manufacturing is getting blurred and hence not many will opt for the traditional COT approach. Foundries will (and are) moving up in the design value chain.

With DFM, there is an increased need for foundries to share process information so that it’s taken into account during the design phase. Foundries collaborating with EDA vendors for this result into tools handling the yield issues while making it as transparent to the designer as possible. Design flows were devised and verified with specific tools (from single or multiple EDA vendors/sources) to tackle various design issues and facilitate FTSS. Now the verification of these flows includes another variable – foundry. i.e. a designer will need to know which foundry’s data has been used to verify the design flow before he starts using it.Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty. There will be an economical need for them to see their foundries operate at capacity. For this, they will need to facilitate new designs in these technos; and hence they will be compelled to either share more information/collaborate or do every thing on it’s own i.e. a one stop shop.

Going to the next technology node has had a triple advantage – reduced power, higher speed and reduced cost due to lower die size. But as we go from 90nm to 65nm and further below, this shrink is leading to only a speed advantage. Leakage, signal integrity & yield issues have reduced the other two advantages. So, we’ll see lesser designs migrating to or starting up in these new technos. And this is besides the high costs involved (for design, mask etc.). Foundries like TSMC are spending a lot of money to build new fabs to handle these advanced nodes’ designs. So, after having invested a fortune, they can not let them be empty.

To sell wafers, one needs tapeouts. Successful tapeouts require libraries and IPs validated on the target technology. And as technology advances, customers are more and more wary of getting their designs taped out with libraries and IPs not fully validated on silicon. So where does this lead a foundry with a ready advanced process but waiting for library & IP vendors to provide their wares on this new techno so that it can get customers’ designs in ?

Well, it provides libraries and IPs - either on it’s own or with partnerships. TSMC’s Europe Technical Director, Douglas Pattullo said in the IP/SoC conference in Grenoble on 7th Dec – TSMC is a provider not just of libraries but of complex IPs as well. He mentions that they are doing it to support their wafer manufacturing biz and not to get a new revenue stream.

It was once the same with EDA vendors. Quite a few of them started providing an IP portfolio – yes, to support their EDA biz. After all, customers are more comfortable with 3rd party IPs proven to be working in a specific design flow. But then as the process world started getting interleaved with the design world & the design space became abuzz with terms like DFM, DFY etc., the impact of foundry information on the EDA and IP space gained further importance.

So, are we headed towards a landscape dominated by a few major players (with deep pockets & partnerships) sporting One-Stop-Shops & dotted by smaller players excelling in niche areas say point EDA tools, special IPs ?

Mentors’ CEO Walden Rhines’ interview in Electronic Times (posted on 2/12/05) brought out 2 interesting points in the EDA industry :

First is on the EDA industry growth which Rhines attributes mainly to developing new solutions to new problems, developing new methodologies & applying technology to different applications. With a very small growth in the number of designers and with tools and methodology in place, design companies do not tend to spend so much in purchasing that many new licenses/seats.

The second interesting point is about start-ups. Usually started by professionals from the major EDA companies/design companies when they see issues/loops in the design flow which they feel they can plug in much better than the existing tools. With the market growing more and more towards point tools and now towards an open platform, they focus on a niche issue. While they contribute a little over 20% of the market revenue, they do represent a major chunk of the EDA methodologies mindshare. And excepting a few of them who have a solid business plan in addition to the strong technology base, most get acquired by the major EDA companies - and spur their growth.

While most other competitors foresee more growth in China, Cisco sees an edge in India and is investing heavily there. The things going for India include an unregulated economy, less competitive environment & a growing market . It’s worries in China include weaker IP protection laws and an edge to home grown local companies like Huawei, Harbor Networks etc. through loans and government support.

The Cisco-ZTE co-operation agreement will let Cisco take advantage of ZTE’s position in the local service provider market and it’s customer knowledge.

One of the potential solutions in addressing the challenges in manufacturing sub 90nm is in greater collaboration. How many of the existing top semiconductor companies can afford to be profitable while keeping their legs in both chip design as well as optimal yield DSM manufacturing ? One needs to focus upon ones’ strengths while leveraging with ones’ partners on others. Partnerships are extending; it’s a need & not just an option.

It makes me reflect on an article posted in Silicon Strategies on 12/27/2004, “15 predictions for IC, equipment biz in 2005 and beyond” which had a compilation of 15 predictions for the IC and chip-equipment industries in 2005 and beyond and listed some foundry marriages.

The sifting is being done……..

Market research company, iSuppli Corp noted in a recent article posted in Electronic Engineering Times by Peter Clarke that India’s semiconductor design industry will nearly triple by 2010; it’s predicted to be 624M$ in ’05.

Investment in India needs to be for a long term strategic reason. Companies jumping into the bandwagon solely for cost reduction will most likely lose out. Some of the very factors driving the growth of the semiconductor industry here e.g. low cost design talent, strong education infrastructure and rapidly growing local market lead to challenges like high attrition rate. While money is a major factor for employee retention, career growth conducive work environment with interesting & innovative work on latest technology will help.

The other challenge of lack of trained designers is being addressed by the industry along with academia leading to several training start-ups which deliver mid & short term courses for fresh engineering graduates as well as working executives for VLSI careers.

The volumes need to justify the high costs involved in 45 nm. Costs include the mask cost (with 2 M$ not being ruled out), design challenges, variability & yield issues to count a few. The consumer market is the major drive for cost reduction and high volumes. However, it needs to be kept in mind that the market windows in this segment are shrinking. To capitalize on these high volumes, chip vendors need to be nimble enough to get the 45 nm product out in time – a feat which is getting tougher as one scales down in the DSM zone.

As noted by John Martin, Chartered Semiconductors, in an article posted by Richard Goering in EE Times, “the costs of 45 nm will raise the stakes.” First Time Silicon Success will be a necessity, not a target.

Improvement in cost per function has always been the driving factor for geometric scaling. It will be the same for 45 nm; in fact much more so keeping in mind the high stakes.

No doubt designers will be able to leverage, to some extent, their investments through reusable architectures and IP. Hopefully, this will expedite an efficient development, verification & hand-off of re-usable architectures and IPs.

Excessive guardbanding should not cut back the gains arising from the scaling to this technology.

As it’s predecessors, the geometrical scaling to 45 nm is increasing challenges, increasing the need to work together, opening up new & niche biz avenues for start-ups (as well as existing companies!) & providing the impetus for different entities in this eco-system to clean up their act or be left behind……..

The microelectronics industry owes much to Moore’s Law – the number of transistors on a chip double every 2 years. It’s a principle which has been solid and consistent for the last 3 decades.

In an article posted by Bill Roberts in Electronic Business, Satoru Ito, CEO of Renesas Technology says. “Because of Moore’s Law, the industry has had a common road map for technological innovation. This allows partnerships and planning for investment.”

It’s an economic barometer with geometric scaling transforming to economic scaling.

Moore’s Law has led to partnership. For no single entity, no matter how deep it’s pockets are and how well entrenched it is with brain power, can work out on it’s own the complexities in the microelectronics ecosystem paved by this law.

It has led to specialization. Semiconductor equipment materials, foundries, EDA, Contract manufacturing, IPs, yield management processes – it has spawned them all. It has spurred entrepreneurial culture without which technology’s potential could not have been realized. And with specialization and innovation not recognizing any geographical boundaries, it has further led to globalization. Biz interests make you go where there is infrastructure, cost saving, brain power, innovation – strategy reason. Moore’s law has sustained because it’s driven by pure economics. Geometric scaling is a prelude to diminishing the cost.

And it has also led to the omnipresent question - after Moore’s Law, what ???

It’s heartening to note Indian government’s proactive stance in putting India’s footprint on the hardware arena too. Several multinationals have a design/R&D setup in India. While most initially came for the comparatively cheap manpower, they’ve stayed put for the brain power and are now investing for innovation. Several local services and product companies too have sprung up. But what has been lacking is an efficient semiconductor manufacturing base i.e. fabs & testing entities. Developing and sustaining them is a formidable task as it’s an extremely capital (& commitment) intensive zone.

Taiwan’s ITRI is a good example to follow in guiding the technological and economic growth of the country. ITRI lists establishing new High tech industry, upgrading traditional industries, leading the drive for sustainable growth and developing highly skilled human resources under their industrial impact. It has played a vital role in turning this island state into a semiconductor hub housing world’s top two foundries and boasting of highly skilled designers.

IBMs’ VC Group’s strategy outlines a varying and rewarding approach to the functioning of a ventures capital arm of a large company. Deviating from the well trodden path of investing cash for ROI, it is emphasizing more on relationships, interests’ alignment and development of a mutually supported ecosystem.

As IBM Corp. VP & MD of it’s VC group, Claudia Fan Munce, stresses in an article in EE Times, the access IBM gains to companies in emerging technos and geographies is worth much more than the return on the cash itself. IBM’s involvement with VC firms and startups aids it in setting it’s technology agenda and pushing it through.

Especially in Asian countries where the right networking/connections building (or guanxi as is called in Chinese) is so important for biz growth, this strategy looks more effective than the relatively “cold” dollars vs return.

With consumer electronics joining PCs and internet based communications as a major semiconductor industry driver, fabs are getting into another league – Gigafabs. TSMC’s Mark Liu differentiates between the fabs on the basis of monthly wafers capacity – 80 to100K qualify as gigafabs while megafabs have a run rate of 50k wafers.

Consumer electronics market has a very short market window including a steep ramp up and leaves little room for redesigns. High price elasticity ranges encompass some real high priced niche products on one end and basic generic commodity tagged products on the other – and both categories can lead to massive volumes if the timing/placing-features-price combo target is hit.

Gigafabs help here because no vendor would like to be placed in a position where he has hit the market with the right product at the right time only to run out of fab capacity – a major biz opportunity loss. Also chips produced cheaper in the fabs (an advantage of gigafabs) can be sold cheaper. While gigafabs help to spread out the costs, not all players can join in due to the high costs involved.