Topic outline

  • Synopsis

    Want to get a head start to your VLSI design career?

    For a relatively fresh (0-3 years) design engineer :
    You may often be awed or sometimes puzzled as to what exactly are the various stages in chip design followed in the industry. How do the specifications translate into a physical chip? Where does your part of the design flow get its inputs from and where are its outputs used? Where does your part fit into the chip design jigsaw puzzle. A basic sound understanding & a holistic view of the complete VLSI chip design flow is what is required here. Additionally, knowing this helps one in planning one's design career path - which design aspect should I specialize in?

    As a design engineer experienced in a certain aspect - be it logic simulation or physical placement or verification or others:
    How does a design decision made in one part of the flow impact your design part and vice versa? To be an efficient and effective design engineer, it is essential to have an understanding of the complete design flow. It surely does diminish the chances of missing out on your First Time Silicon Success!

    As a chip design Program Manager, Customer support, Business Development:
    Needless to say here, one would require a sound know-how of the complete design flow to be effective in these roles.

    This course is aimed to provide an opportunity for the participant to acquire comprehensive technical and industry relevant insight into the VLSI IC Design arena. 

    This course will provide a basic understanding & a holistic view of the complete VLSI chip design flow. It will enable the participant to understand the basics involved in various phases of IC design with an appreciation of the links and dependencies across them. Industry insights shared in this training help the participant appreciate the IC design flow in a real working world.

    The course is structured into modules. Participants will be exposed to issues cited from real industry experience.  This course is delivered by a senior VLSI consultant with extensive exposure in supporting & managing IC projects on a global scale.

    The classroom version of this course spans 3 days. But of course, you have the luxury to go through this e-learning version at your pace and at your convenience!

  • What you will learn

    After going through this training, the participant would have learnt different aspects and phases of the complete IC design flow

    These include

    • Basics of design library
    • Logic simulation and synthesis
    • Floor plan, Place & Route, Design for Manufacturability
    • Design Verification, Design for Testability
    • Low power design methodologies
    • Dependencies and links across various design phases – this, in turn, will facilitate him/her in comprehending how decisions made in one phase affects the other
    • Be ready to handle specific and further details of each design phase
  • Who should enrol

    • EEE engineers working in IC design (0 - 3 years experience)
    • Engineers experienced in 1 domain of the IC design flow and who would like to understand better the other phases of the flow
    • Customer support engineers, Business Development engineers, Program Managers who would like to get a detailed and holistic overview of the complete chip design flow
  • Pricing and Terms & Conditions

    How to purchase access to this e-learning session?

    • Select your package
    • Register (as per instructions in the Register tab below)
    • On receiving acknowledgement email of successful registration from VLSI Consultancy, pl. proceed with the payment as outlined in the acknowledgement email. 

    Pl. feel free to contact us in case of any clarifications.

     

  • Training Introduction

    Welcome to the e-learning session for "VLSI Digital Design Essentials".

    The original format for this training is a classroom training spanning 3 days. The same has been modified to facilitate e-learning. We do have a detailed 4 days session too on this training.

    For a list of our classroom trainings, pl. refer to http://www.asic-vlsi.com/training.html

    This introduction module of the e-learning session includes a Training Introduction part and a Pre-training Quiz.

    Wish you an interesting and informative learning session!!

  • Module 1: Introduction

     

    What you will learn

    • Basics of IC Design Flow
    • Some definitions
    • Generic Technology Aspects & Trends
  • Module 2: Design Library

     

    What you will learn

    • Definition, Library Architecture (with basic introduction to SSIs, IOs, Memories, IPs; general circuits used like Flip flops, latches, combinational circuits, RAMs, ROMs etc. will be included)
    • Library Cell Representations
    • Cell views (logical description, timing information, derating data, capacitance information, power and area information)
    • Global views (max capacitance, interconnect info, max power and derating information)
    • Library Characterization
    • (Standard load, trip points, parasitic caps, input slew rate, timing equation, delay calculation)
    • Library Validation
    • Trends in Library architecture
    • (Power, speed optimization, drive, contents changing with technology and trends)
  • Module 3: Logic Simulation & Synthesis

     

    What you will learn

    Logic Simulation

    • Simulation modes (behavioral, functional, static timing analysis, gate level simulation)
    •  Net capacitance
    • Cell model (primitive, library, macro/IP) and test bench
    • SDF in simulation
    • Limitations of logic simulation
    • STA

    Logic Synthesis

    • Logic synthesis in the design flow
    • HDL and Synthesis – some HDL guidelines
    • Constraints and Operating conditions
    • Memory Synthesis
    • Timing driven synthesis
  • Module 4: Floorplan, Placement & Routing, Finishing and DFM

     

    What you will learn

    Floorplan

    • Goal, objective
    • Hierarchical Design
    • I/O and Power planning
    • Core limited and pad limited design
    • Clock Planning
    • Grouping and Regioning

    Placement & Routing, Finishing

    • Goals  & Objectives
    • Timing driven placement/Physical Design flow
    • Information formats
    • Routing (Global & detailed routing, clock routing, power routing)
    • Back Annotation, Circuit extraction
    • Design checks, Mask preparation

    Design For Manufacturability (DFM)

    • Need for DFM
    • Yield categories
    • Yield Optimization (Critical Area Analysis, Chemical Mechanical Polishing, Lithography Compliance Check)

  • Module 5: Verification & Design For Testability (DFT)

     

    What you will learn

    Verification

    • Need for Verification
    • Functional Verification (Simulation, Formal Verification, Coverage – Code, Functional, Assertion)
    • Timing Verification – STA, SSTA
    • Physical Verification – DRC, LVS, Parasitic Extraction

    Design For Test (DFT)

    • Scan (Full scan, boundary scan)
    • Faults – Fault models, Fault collapsing, IDDQ test and Fault simulation
    • ATPG, At speed test
    • BIST (LFSR, Signature Analysis)
    • Test logic insertion
  • Module 6: Low Power Design Guidelines

     

    What you will learn

    • Sources of power dissipation (Static, Short circuit, dynamic)
    • Power distribution considerations (Temperature, package, Voltage drop, Electromigration)
    • Low power design techniques and methodologies (levels of low power optimization, includes, MSV, MTCMOS, VTCMOS, encoding, logic reduction, clock gating etc.)
    • Guidelines for low power design
  • Training Wrap-up

    This includes Training Recap and Post Training Quiz.

    Hope you have enjoyed this e-learning session with us.

    Should you have any questions to ask/clarify, pl. email me at meenu@asic-vlsi.com and we can arrange to align and address this as per the Terms & Conditions of the e-learning package you've purchased

    Thank you and wish you all the best!